In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels of the transistors, and which are typically on the order of tens of nanometers in width.
In these fin type devices, the transistor is formed in part in a fin rising out of a planar background, typically having both vertical and horizontal surfaces. The gate of the non-planar device may engage the vertically oriented body surfaces, or sidewalls, of the fin, and the top surface as well, resulting in several planes being used for transistor channel formation. In other typical non-planar devices the gate of the non-planar device may not engage the top surface, only the vertically oriented body surfaces. There are further variations of non-planar devices, for instance, some with multi-faceted fins and multiple sidewall sections.
A typical FinFET, as fabricated and used presently in the art, has a symmetric structure, meaning that the FET devices on each side surface of the fin are essentially identical with one other, having same device characteristics. However, for some applications, it is desirable to have an asymmetric, multi-gated FinFET. For instance, depending on the power supply, the characteristics of the asymmetric FinFET can be adjusted to achieve an optimal trade-off between power consumption and device performance. For example, when the FinFET is powered by a battery, low power consumption requirements usually outweigh performance requirements. On the other hand, when the FinFET is powered by an external AC supply, high performance is usually desired. In FinFETs where the gate structure is asymmetric, one gate is typically referred to as the “front gate” (FG) and the other gate is typically referred to as the “back gate” (BG).
Fabricating asymmetric, multi-gated FinFETs may be possible with complicated and costly methods. Such complicated and costly methods typically require additional masking steps compared to fabricating symmetric, namely essentially identical, FET devices on semiconductor fins. Furthermore, the small-scaled fins that are presently used in the art and that are planned in the future are narrow, rendering overlaying masks very difficult.
It would therefore be desirable to have asymmetric FinFET devices with improved methods for forming them, which methods would be similar in complexity and in cost to fabricating traditional, symmetric FinFET devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.